Memory capacity
Memory modules
The number of individual modules included in RAM kit. One module occupies one slot on the motherboard, so to install the entire kit, the number of free slots must be equal to or greater than the number of modules.
If there is an even number of modules in the set, they can be paired. This mode significantly increases the speed, but is not supported by all models of motherboards, so in each case this point should be clarified separately.
Now on the market? there are modules supplied in such quantity:
one modules,
set of 2 modules,
set of 4 modules,
set of 8 modules.
CAS latency
This term refers to the time (more precisely, the number of memory cycles) that passes from the processor's request to read data to granting access to the first of the cells containing the selected data. CAS latency is one of the timings (for more details, see the "Memory Timings Scheme" section, where this parameter is designated as CL) — which means that it affects performance: the lower the CAS, the faster this memory module works. However this is true only for the same clock frequency (for more details, see ibid.).
Now there are memory modules on the market with the following CAS latency values:
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
24,
28,
30,
32,
36,
38,
40,
42,
46.
Memory timing
Timing is a term that refers to the time it takes to complete an operation. To understand the timing scheme, you need to know that structurally RAM consists of banks (from 2 to 8 per module), each of which, in turn, has rows and columns, like a table; when accessing memory, the bank is selected first, then the row, then the column. The timing scheme shows the time during which the four main operations are performed when working with RAM, and is usually written in four digits in the format CL-Trcd-Trp-Tras, where
CL is the minimum delay between receiving a command to read data and the start of their transfer;
Trcd — the minimum time between the selection of a row and the selection of a column in it;
Trp is the minimum time to close a row, that is, the delay between the signal and the actual closing. Only one bank line can be opened at a time; Before opening the next line, you must close the previous one.
Tras — the minimum time the row is active, in other words, the shortest time after which the row can be commanded to close after it has been opened.
Time in the timing scheme is measured in cycles, so the actual memory performance depends not only on the timing scheme, but also on the clock frequency. For example, 1600 MHz 8-8-8-24 memory will run at the same speed as 800 MHz 4-4-4-12 memory—in either case timings, if expressed in nanoseconds, will be 5-5-5-15.
